A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of devices and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
FIG. 1 is a flow diagram illustrating a conventional process for etching a semiconductor wafer to form the memory gate stack 10 of FIG. 2. The memory gate 10 includes therein a suitable semiconductor substate 52 having a top surface 54 and a gate stack 70. The gate stack includes a tunnel oxide layer 56 (i.e., a standard-K dielectric layer) which separates a floating gate 58 firm the substrate 52. In some embodiments, it is both desirable and advantageous to form tunnel oxide layer 56 from a mid-K or high-K dielectric material.
An interpoly dielectric 60 separates the floating gate 58 from a control gate 62. The floating gate 58 and the control gate 62 are each electrically conductive and typically formed of polysilicon. On top of the control gate 62 is a silicide layer 64, which acts to increase the electrical conductivity of control gate 62. The silicide layer 64 is typically a tungsten silicide (e.g., WSi2), that is formed on top of the control gate 62 prior to patterning, using conventional deposition and annealing processes.
The method shown in FIG. 1 begins in step 10, where the multi-layer semiconductor wafer including the polysilicon layer 58, the ONO layer 60, the polysilicon layer 62, the silicide layer 64, and an oxide cap layer 66 overlying the silicide layer is covered with a photoresist layer. It should be noted that the oxide cap layer 66 is optional and need not be included if so desired.
The photoresist layer is patterned in step 12 to form a mask to form the memory gate in step 12. The semiconductor wafer is then inserted into an oxide etch chamber in step 14, and an oxide etching operation is performed on the regions of the silicon oxynitride layer 66 exposed by the mask. The semiconductor wafer is then moved in step 16 from the oxide etch chamber to a polysilicon etch chamber, where polysilicon etch processing is performed on the silicide layer 64 and the polysilicon layer 62. The semiconductor wafer is then removed from the polysilicon etch chamber and cleaned in step 18 to remove any remaining resist, and polymers remaining during the etching process. For example, the resist and sidewalls of the etched semiconductor may be cleaned using a hydrofluoric acid dip, plus a dry plasma (O2) clean, followed by a sulfuric acid bath. Following cleaning, another mask is formed in step 20 to cover areas that are not part of a memory core. The masked wafer is then moved to an oxide etch chamber in step 22 for etching of the ONO layer 60. Once the ONO layer 60 is etched, the semiconductor wafer is once again moved in step 24 to a polysilicon etch chamber in step 24 for etching of the polysilicon layer 58, followed by cleaning of the mask in step 26. Finally, in step 28 the tunnel oxide layer 56 (i.e., dielectric layer 56) is etched back using the gate stack 70 as a mask. It will be apparent to one of skill in the art that additional processing steps can be conducted after step 28. However, for brevity, the discussion here of such further steps is omitted.
A problem arises when the tunnel layer 56 is formed from a high-K dielectric material in that the removal rate of most high-K dielectric materials is lower when compared with standard-K dielectric materials (oxides) from which tunnel oxide layer 56 is formed.
Conventional techniques for forming memory gates require a substantial amount of etching in different etching chambers. Such processes require significant amounts of handling of the semiconductor wafers, risking contamination of the wafer during transfers between etching chambers. Hence, there is a need in the art for a method to increase the etch rate of high-K dielectric materials without increasing the number of etching chambers utilized to etch a desired semiconductor device.